Systems in a network environment communicate information in packets that encapsulate the information according to network communication protocols. Packets transmitted from one node to another node may be transmitted through one or more intervening routers that route the packets throughout the network or between networks. The router typically includes one or more network processors to process the packets and may also include a core processor. The network processor stores packets in a memory device, such as a Static Dynamic Random Access Memory (SDRAM). When a packet is added to the SDRAM, an entry, referred to as a buffer descriptor, is added to a packet queue in another memory device, such as a Static Random Access Memory (SRAM), which is used to maintain control information on the packets added to the SDRAM. The SRAM may include multiple queues for packets in the SDRAM.
A network processor may include a plurality of packet engines, also known as microengines, that process and forward the packets being transmitted from one node to another and may also include a core processor to perform other related processing information. In certain prior art network processors having packet engines as well as a core processor, the packet engines may process unicast packets and the core processor may process multicast packets having a payload to transmit to different destination addresses.
Further, when processing a multicast packet, the core processor may write an instance of the multicast packet payload to the SDRAM for each destination address to which the packet is directed. A buffer descriptor may also be created and queued for the entries added to the SDRAM for the destination addresses of the multicast packet. Thus, multiple entries in the SDRAM are used to buffer the same payload sent to the different destination addresses. The entries in the SDRAM include a unique header for the different destination addresses, where the header includes address and other information to route the payload of the multicast packet to the destination address.